Low power dynamic comparator design

Senapati , Prasanta Kumar (2014) Low power dynamic comparator design. MTech thesis.



In many applications there is a growing demand for the development of low voltage and low power circuits and systems. Low power consumption is of great interest because it increases the battery lifetime. One of the main building blocks in many applications is the analogue-to-digital converter (ADC) which serves as an interface between the analogue world and the digital processing unit. In all these designs the comparator of the ADC, which is one the most power hungry blocks, is always on. In order to reduce the power consumption of the ADC it is possible to turn the comparator off when the decision is made and the comparator is not needed until the next clock cycle. This work provides a comprehensive review about a variety of comparator designs - in terms of performance, power and delay. The initial part of the work was working with static comparators architectures with different pre-amplifier modifications .Later part deals with two dynamic comparator architectures. The main components of such comparators are the preamplifier and latch circuit. Preamplifier is used for removing the kickback noise and the dc offset voltage while the latch is required for the comparison. The proposed architectures operate on three phases which are non-overlapping and dissipate 7ìW power when operated on a single 1V supply voltage. The latch is basically a back to back connected inverter circuit which inactivated only during the second phase.

Item Type:Thesis (MTech)
Uncontrolled Keywords:pre-amplifier,latch,self biased differential amplifier,dynamic comparator,gain,offset,propagation delay,
Subjects:Engineering and Technology > Electronics and Communication Engineering > VLSI
Divisions: Engineering and Technology > Department of Electronics and Communication Engineering
ID Code:6386
Deposited By:Hemanta Biswal
Deposited On:10 Sep 2014 14:54
Last Modified:10 Sep 2014 14:54
Supervisor(s):Islam, M N

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