Piparsaniyan, Yamini (2014) FPGA Implementation Of A Novel Robust Facial Expression Recognition Algorithm. MTech thesis.
A facial expression recognition system depicts about state of mind of a particular by showing their emotions, thus has potential application in various field of human computer interaction (HCI) such as to aid autistic children, robot control and many more. This work presents a robust and hardware efficient algorithm for facial expression recognition which gives very high rate of accuracy. Broadly, human facial expression has been categorized in seven categories, named as anger, disgust, fear, happy, sad, surprise with basic neutral emotion. The process of emotion recognition starts with the image capturing, detecting the face in the image of which emotion has to recognize, extracting robust and unique features of image which makes categorization efficient and classification of features for one of the above mentioned emotion categories. Face detection out of an image is done using existing Bayesian discriminating feature method. An algorithm is proposed for facial expression recognition, integrating Gabor filter bank and its features for feature extraction, statistical modelling which uses principal component analysis PCA and conditional density function for modelling of features and extended Bayes classifier for multi-class classification of emotion in a detected face. The multi class classification strategic has been applied based on highest value of log likelihood after training different emotions class. Robust features are extracted using Gabor filter with 8 frequency and 8 orientations. FPGA implementation of the extended Bayesian classifier is done on Xilinx10.1, VirtexIIpro FPGA using CORDIC unit for trigonometric functions. Facial expression images from JAFFE database have been used for training as well as testing. Very high accuracy (96.73 %) of emotion recognition has been obtained with proposed method.
|Item Type:||Thesis (MTech)|
|Uncontrolled Keywords:||Facial expressions; Gabor features; Bayesian classifier; CORDIC; FPGA|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > VLSI|
|Divisions:||Engineering and Technology > Department of Electronics and Communication Engineering|
|Deposited By:||Hemanta Biswal|
|Deposited On:||12 Sep 2014 15:37|
|Last Modified:||12 Sep 2014 15:37|
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