Sahoo, Seemanjali (2014) FPGA Implementation of Circularly Shifted PTS Technique for PAPR Reduction in OFDM. MTech thesis.
In today’s world, the ongoing trend in 4G has adopted multi-carrier transmission schemes like OFDM, OFDMA and MIMO-OFDM. OFDM has proven to be one of the most promising schemes used for transmission of signals. It still exists with some of the drawbacks, out of which, the high peak to average power ratio gives rise to non-linear distortion, inter-symbol interference and out-of-band radiation. There has been various ways developed and implemented to reduce peak to average power ratio. Comparing between all the techniques to reduce peak to average power ratio, it has been found that the best method is partial transmit sequence technique. This technique was first proposed by Muller and Huber in the year 1997. Within the years there have been various modifications with this technique which has been proposed and implemented. Today’s world is a digital world where an analog form of communication can be transformed to digital form of communication. Weste and Skellern were the first to propose the OFDM method in VLSI. The partial transmit sequence technique in FPGA has been proposed by Junjun et.al. and Varahram et.al. In this thesis work an efficient FPGA implementation of circularly shifted partial transmit sequence (CS-PTS) scheme for peak-to-average power ratio (PAPR) reduction in orthogonal frequency division multiplexing (OFDM) signals has been carried out. It eliminates the search for optimum phase factors from a given set, which manifests improved PAPR at reduced computational complexity as compared to conventional PTS (C-PTS). The amplitude of the signal is reduced by rotating each of the partially transmitted sequence anti-clockwise by a pre-determined degree and the peak power is reduced by circularly shifting the quadrature component of the partially transmitted sequence after phase rotation.
|Item Type:||Thesis (MTech)|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > VLSI|
|Divisions:||Engineering and Technology > Department of Electronics and Communication Engineering|
|Deposited By:||Hemanta Biswal|
|Deposited On:||12 Sep 2014 15:51|
|Last Modified:||12 Sep 2014 15:51|
|Supervisor(s):||Patra, S K|
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