Mohanty, Ram Prasad (2014) Studies on the Impact of Cache Configuration on Multicore Processor. MTech by Research thesis.
The demand for a powerful memory subsystem is increasing with increase in the number of cores in a multicore processor. The technology adapted to meet the above
demands are: increasing the cache size, increasing the number of levels of caches and bymeans of a powerful interconnection network. Caches feeds the processing element at a faster rate. They also provide high bandwidth local memory to work with. In this research, an attempt has beenmade to analyze the impact of cache size on performance of multicore processors by varying L1 and L2 cache size on the multicore processor with internal network (MPIN), also referenced from NIAGRA architecture.
As the number of cores increases, traditional on-chip interconnect like bus and crossbar proves to be less efficient as well as suffers from poor scalability. In order to overcome the scalability and efficiency issues in these conventional interconnects, ring based design has been proposed. The effect of interconnect on the performance of multicore processors has been analyzed and a novel scalable on-chip interconnection mechanism
(INoC) for multicore processors has been proposed. The benchmark results are presented using a full system simulator. Results shows that, using the proposed INoC,execution time can be significantly reduced, compared with MPIN.Cache size and set-associativity are the features on which the cache performance is dependent. If the cache size is doubled, then the cache performance can increase but at the cost of high hardware, larger area and more power consumption. Moreover, considering the small form-factor of themobile processors, increase in cache size affects the device size and battery running time. Re-organization and reanalysis of cache onfiguration ofmobile processors are required for achieving better cache performance, lower power consumption and chip area. With identical cache size, performance gained can be obtained from a novel cache mechanism. For simulation, we used SPLASH2 benchmark suite.
|Item Type:||Thesis (MTech by Research)|
|Uncontrolled Keywords:||Catch Configuration; NIAGRA; MIPIN; Memory Subsystem|
|Subjects:||Engineering and Technology > Computer and Information Science > Networks|
|Divisions:||Engineering and Technology > Department of Computer Science|
|Deposited By:||Hemanta Biswal|
|Deposited On:||05 May 2015 10:12|
|Last Modified:||05 May 2015 10:12|
|Supervisor(s):||Turk, A K|
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