Design and Analysis of Improved Domino Logic with Noise Tolerance and High Performance

Meher, Preetisudha (2014) Design and Analysis of Improved Domino Logic with Noise Tolerance and High Performance. PhD thesis.



The demands of upcoming computing, as well as the challenges of nanometer-era of VLSI design necessitate new digital logic techniques and styles that are at the same time high performance, energy efficient and robust to noise and variation. Dynamic CMOS logic gates are broadly used to design high performance circuits due to their high speed. Conversely, the vital demerit of dynamic logic style is its high noise sensitivity. The main reason for this is the sub-threshold leakage current flowing through the pull down network. With continuous
technology scaling, this problem is getting more and more severe. In this thesis, a new noise tolerant dynamic CMOS circuit technique is proposed. In the proposed work, we have enhanced the behavior of the domino CMOS logic. This
technique also gets benefit in terms of delay and power. This thesis describes the new low power, noise tolerant and high speed domino logic technique and presents a comparison result of this logic with previously reported schemes. Simulation results prove that, in 180 nm CMOS technology when we used this logic style to realize wide fan-in logic gates, it could achieve maximum level of noise robustness as compared to its basic counterpart. In addition, the logic also works efficiently with sequential circuits. The feasibility of this new technique is demonstrated by means of a real hardware,
we have built a custom test-chip in the UMC 180 nm process technology with an ALU core, using the proposed domino logic style for each design block. In this thesis, we have also described the design and implementation of this chip. In addition to this, we have also presented initial power and delay performance comparisons between the circuit level simulated ALU and test-chip implemented in the proposed domino logic style. Finally we conclude that, the thesis contributes a very efficient logic style for wide fan-in gates, which is not only noise robust but also energy efficient and high speed.

Item Type:Thesis (PhD)
Uncontrolled Keywords:Domino Logic, Noise Tolerance, High Performance
Subjects:Engineering and Technology > Electronics and Communication Engineering > Data Transmission
Divisions: Engineering and Technology > Department of Electronics and Communication Engineering
ID Code:6658
Deposited By:Hemanta Biswal
Deposited On:19 May 2015 15:56
Last Modified:19 May 2015 15:56
Supervisor(s):Mahapatra, Kamalakanta

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