Panda, Manisha (2015) Performance Evaluation of XY and XTRANC Routing Algorithm for Network on Chip and Implementation using DART Simulator. BTech thesis.
In today’s world Network on Chip(NoC) is one of the most efficient on chip communication platform for System on Chip where a large amount of computational and storage blocks are integrated on a single chip. NoCs are scalable and have tackled the short commings of SoCs . In the first part of this project the basics of NoCs is explained which includes why we should use NoC , how to implement NoC ,various blocks of NoCs .The next part of the project deals with the implementation of XY routing algorithm in mesh (3*3) and mesh (4*4) network topologies. The throughput and latency curves for both the topologies were found and a through comparison was done by varying the no of virtual cannels. In the next part an improvised routing algorithm known as the extended torus(XTRANC) routing algorithm for NoCs implementation is explained. This algorithm is designed for inner torus mesh networks and provides better performance than usual routing algorithms. It has been implemented using the CONNECT simulator. Then the DART simulator was explored and two important components namely the flitqueue and the traffic generator was designed using this simulator.
|Item Type:||Thesis (BTech)|
|Uncontrolled Keywords:||routing algorithm,NoCs ,flitqueue, DART simulator,XTRANC,software implementation,traffic generator,router|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > VLSI|
|Divisions:||Engineering and Technology > Department of Electronics and Communication Engineering|
|Deposited By:||Mr. Sanat Kumar Behera|
|Deposited On:||09 Mar 2016 11:39|
|Last Modified:||09 Mar 2016 11:39|
|Supervisor(s):||Swain, A K|
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