Dasari, Srikanya (2015) Virtual Fabrication of Recessed-Source/Drain SOI MOSFETs. BTech thesis.
The main objective of using process simulator in the IC fabrication technologies is to obtain the fast and accurate simulation of all critical fabrication steps used in the semiconductor devices. ATHENA process simulator provides an appropriate and suitable platform for simulating processes such as oxidation, lithography, physical etching and deposition, diffusion, ion implantation which are used in the semiconductor industry. Scaling down of MOSFET device in IC Technology offers excellent features. However, leakage current and short channel effects (SCEs) are to be considered when MOSFETs are scaled to the deep submicron region. A Re-S/D SOI MOSFET with 30nm channel length, and 10nm channel thickness, is virtually fabricated using ATHENA process simulator with reduced short channel effects (SCEs) and low source/drain series resistance. The processing steps, which are required to obtain the structure of the Re-S/D SOI MOSFET, are explained in detail. The electrical characteristics such as drain current (Ids) versus drain to source voltage (VDS) is obtained for different values of VGS and Re-S/D thickness (trsd). The influence of gate oxide thickness, recessed source/drain thickness on subthreshold swing is observed and analyzed. Further, performance of the device is improved by a gate engineering technique named dual metal gate technology. This technique is incorporated in the virtual fabrication of single metal gate recessed source/drain SOI MOSFET. The effect of channel length ratio on threshold voltage (Vth), surface potential, subthreshold current (Isub) and drain current (Ids) is observed. Also the impact of recessed source/drain thickness (trsd) on drain current (Ids) is evaluated.
|Item Type:||Thesis (BTech)|
|Uncontrolled Keywords:||Process Simulator, Re-S/D SOI MOSFET, Dual Metal Gate Technology, Short Channel Effects|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > VLSI|
|Divisions:||Engineering and Technology > Department of Electronics and Communication Engineering|
|Deposited By:||Mr. Sanat Kumar Behera|
|Deposited On:||15 Mar 2016 17:09|
|Last Modified:||15 Mar 2016 17:09|
|Supervisor(s):||Tiwari, P K|
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