Adiabatic Logic Design for Low Power VLSI Applications

Sahu , Kiran Kumar (2015) Adiabatic Logic Design for Low Power VLSI Applications. BTech thesis.



A conventional CMOS logic circuit design approach depends upon charging the output capacitive nodes to the supply voltage or discharging it to the ground. This is one of the most used methods in VLSI designs. There are various techniques to design low power circuits both at system level as well as at circuit level to reduce power consumption. One of the major source of power dissipation is the charging and discharging of capacitor. Every time when a capacitor is discharged to ground, an amount of energy = ½ C stored in the capacitor is lost. We can reduce this power dissipation by restoring this energy to the source instead of discharging to the ground. Another way of reducing the power dissipation is to design the circuit in such a way that the charging of the capacitive node takes place very slowly. It has been observed that by charging the capacitor slowly, the energy require is lesser than faster charging method. Adiabatic circuits use the above two methods viz. slow charging of capacitor and discharging, and recycling of charge to minimize the power consumed. Several Adiabatic designs have been designed and tested in this paper. Most of them achieve significant power savings in comparison to conventional CMOS designs. The major drawbacks of these circuits include complex design for achieving simple operations, requirement of multiple clocks and requirement of complimentary input signals for controlling the charging and discharging process. The Current work is based on an existing adiabatic logic style known as PFAL (Positive Feedback Adiabatic Logic) and ECRL (Energy Efficient Charge Recovery Logic) which are simple and doesn’t require complimentary signals or complex clocking. “ A simulative investigation on the proposed 1-bit full adder has been implemented with the proposed technique and hence compared with standard CMOS, Positive Feedback Adiabatic Logic (PFAL), Static Energy Recovery Full Adder (SERF), 8T Full Adder and 9T Full Adder respectively. We compared all the designs and achieved a significant power saving to the extent of 40% in case of proposed technique as compared to CMOS logic in 50 to 200MHz transition frequency range. Later in this paper I have implemented the carry look-ahead adder based on adiabatic logic and got a faster response up to 100ps as compared to Full adder counterpart. A comparative result has also been shown by a graph which represents the least power dissipation of proposed technique. In this paper all circuits are analysed in terms of power using 90nm technology and simulated using cadence virtuoso and Tanner EDA.

Item Type:Thesis (BTech)
Uncontrolled Keywords:Adiabatic logic,SERF, PFAL, ECRL, Carry-look-ahead adder
Subjects:Engineering and Technology > Electronics and Communication Engineering > VLSI
Divisions: Engineering and Technology > Department of Electronics and Communication Engineering
ID Code:7267
Deposited By:Mr. Sanat Kumar Behera
Deposited On:21 Apr 2016 21:38
Last Modified:21 Apr 2016 21:38
Supervisor(s):Islam, M N

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