Mohapatra, Soumen (2015) An Optimization of 16×16 SRAM Array for Low Power Applications. BTech thesis.
SRAM being Robust and having less read and write operation time is intended to use as a cache memory which oblige low power utilization. Low power SRAM outline is critical because it takes a vast division of aggregate power and pass on region in superior processors. A SRAM cell must meet the prerequisites for the operation in submicron/nano ranges. The scaling of CMOS innovation has critical effects on SRAM cell – arbitrary variance of electrical qualities and significant leakage current. The paper introduces the configuration of 16×16 SRAM array design including row decoders/drivers, column circuitry, sense amplifiers, pre charge circuitry and transmission gates utilizing Cadence tools in a unique way and its functionality is analyzed properly.
|Item Type:||Thesis (BTech)|
|Uncontrolled Keywords:||Sense Amplifier,Transmission Gate,SRAM Array|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > VLSI|
|Divisions:||Engineering and Technology > Department of Electronics and Communication Engineering|
|Deposited By:||Mr. Sanat Kumar Behera|
|Deposited On:||23 May 2016 12:41|
|Last Modified:||23 May 2016 12:41|
|Supervisor(s):||Islam, M N|
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