Singh, Ashutosh Kumar (2015) ASIC implementation of FFT Engine for Audio Driver. MTech thesis.
Dynamic performance of the audio system is characterized by the parameters, SNR, SNDR, THD, SFDR and DC Componentin the signal. By measuring these parameters dynamically, suitable action can be taken to maintain these parameters within its limited value. This will increase the dynamic performance of audio system. The thesis work is divided into five parts, first is modeling of entire system in MATLAB and selecting the suitable algorithms to compute FFT and different dynamic parameters (SNR, SFDR, THD, SNDR, Percent THD plus Noise, DC component), second is making a top level model in Simulink in hardware prospective where we can replace each algorithm with corresponding block consisting of required hardware, third is making the entire top level model from floating point model to fixed point model where we can decide the processing capacity and data width of each hardware (A fixed point model a design in MATLAB is very close to a RTL model of a Digital design ), fourth step is to generate a synthesizable Verilog code using MATLAB HDL Coder for entire top model and final step is verification of generated RTL model in ModelSim by comparing it with standard MATLAB results. Our final aim is to design the system for Audio driver application which range is 20 Hz to 20 kHz, since we can verify the the system more accurately if we consider the whole range of frequency bin (zero to half of the sampling Frequency) so we have designed to desperate model, one for audio range and another for full range. Designed system can accurately measure 100 dB SNDR (based on observation). FFT engine has been designed for 65536 points (216 points) and input data width is 16 bit. Internal structure of FFT engine is designed to process 32 bit data. Fixed point algorithm is completely parametrized ( Except few miner changes in CORDIC block) for input data width. We can also increase the number of FFT points, but it will increase the requirement of RAM. There is a huge high level resource utilization in comparison to HDL optimized FFT block given by MATLAB. Number of required multipliers is almost half of HDL, and only two RAMs (65536 x 32 bit) is required to implement the entire system where only HDL optimized FFT block itself needs 34 RAMs of different sizes including two 65536 x 32 bit RAMs. We are using CORDIC algorithm to implement CORDIC multiplier, Absolute block and Logarithmic block. Due to the use of CORDIC multiplier there is no need of real multipliers (except angle multipliers) in CORDIC butterfly and also there is no need to store the twiddle factors in separate ROMs.
|Item Type:||Thesis (MTech)|
|Uncontrolled Keywords:||SNR, SNDR, THD, FFT, Analysis block, SFDR, FFT engine, Fixed point modeling|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > VLSI|
|Divisions:||Engineering and Technology > Department of Electronics and Communication Engineering|
|Deposited By:||Mr. Sanat Kumar Behera|
|Deposited On:||13 May 2016 11:20|
|Last Modified:||13 May 2016 11:20|
|Supervisor(s):||Acharya, D P|
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