Design and Analysis of Efficient Phase Locked Loop

Abstract

Phase Locked Loop is one of the most important component in design of almost all electronic goods . In modern communications PLL circuit has a wide applications in radio, telephone, mobile phone, PCs and other electronics applications. Phase Locked Loops are used for synchronization , synthesis of clock and jitter reduction in mobile or wireless communications. Due to the increment in the rate of the circuit operation, there is a need of a PLL circuit with quicker locking capacity. PLL is designed to operate both for analog and digital signal processing. For demodulating a signal and recovering it to its original input signal, PLL circuit is used. PLL has a wide application in higher frequency ranges (GHz) as they lock the frequency in less span of time. The main theme of the work is to design a Phase Locked Loop. PLL is designed in CADENCE Virtuoso Analog Design Technology using 90nm process Technology (GPDK90). For this a Current Starved Voltage Controlled Oscillator has been taken with which the required frequency is obtained at certain voltage