Design and Analysis of Efficient Phase Locked Loop

Naik, Malothu Dilip Kumar (2015) Design and Analysis of Efficient Phase Locked Loop. BTech thesis.



Phase Locked Loop is one of the most important component in design of almost all electronic goods . In modern communications PLL circuit has a wide applications in radio, telephone, mobile phone, PCs and other electronics applications. Phase Locked Loops are used for synchronization , synthesis of clock and jitter reduction in mobile or wireless communications. Due to the increment in the rate of the circuit operation, there is a need of a PLL circuit with quicker locking capacity. PLL is designed to operate both for analog and digital signal processing. For demodulating a signal and recovering it to its original input signal, PLL circuit is used. PLL has a wide application in higher frequency ranges (GHz) as they lock the frequency in less span of time. The main theme of the work is to design a Phase Locked Loop. PLL is designed in CADENCE Virtuoso Analog Design Technology using 90nm process Technology (GPDK90). For this a Current Starved Voltage Controlled Oscillator has been taken with which the required frequency is obtained at certain voltage

Item Type:Thesis (BTech)
Uncontrolled Keywords:Phase Locked Loop,syncronization,locking capacity and CADENCE virtuoso
Subjects:Engineering and Technology > Electronics and Communication Engineering > Wireless Communications
Engineering and Technology > Electronics and Communication Engineering > VLSI
Divisions: Engineering and Technology > Department of Electronics and Communication Engineering
ID Code:7479
Deposited By:Mr. Sanat Kumar Behera
Deposited On:13 May 2016 10:10
Last Modified:13 May 2016 10:11
Supervisor(s):Acharya, D P

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