Sailaja, Saragadam (2015) Automation of Analog Circuit Designing and Simulation. MTech thesis.
With the advent of sub-micron CMOS process technologies, application of drain current model equations alone, which is good for long-channel devices, to design an analog circuit is becoming futile. So, the design of analog circuits is the time-limiting bottleneck, in comparison with the digital counterparts, of the mixed IC signal designs. Shortage of analog integrated circuit design automation tools results in relying on engineering experience and time-consuming trial-and-error simulation runs to design an analog IC. The research presented in this thesis aims to improve the efficiency of analog IC design process with a new design methodology. This new methodology is mainly based on the smallsignal analysis and designers' experience on how to achieve the desired specifications. A CAD tool is also developed to characterize the devices such as MOSFETs, Resistors, and Capacitors, which is useful to follow the newly developed design methodology. To demonstrate the usefulness and reliability of the new methodology and the tool, some design examples are also presented. This thesis has also given the study report on existing analog IC design automation methods. Apart from the design automation, another major time-consuming constraint is to do the Simulation for existing designs, mainly if it requires multiple analyses to be performed to extract the required parameters. This issue is also addressed in this thesis, to some extent, by taking a test-case of VCO circuit.
|Item Type:||Thesis (MTech)|
|Uncontrolled Keywords:||Analog Designing, IC designing, Design automation, Current Mirror circuit, Differential amplifier, VCO, Design simulation, Simulation of VCO circuit, Automation approaches|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > VLSI|
|Divisions:||Engineering and Technology > Department of Electronics and Communication Engineering|
|Deposited By:||Mr. Sanat Kumar Behera|
|Deposited On:||12 May 2016 18:33|
|Last Modified:||12 May 2016 18:33|
|Supervisor(s):||Acharya , D P|
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