Hardware Trojan Detection in Third Party Digital IP Cores

Chanamala, Rakesh (2015) Hardware Trojan Detection in Third Party Digital IP Cores. MTech thesis.



Due to Globalization outsourcing of SoC designs either for verification, testing and fabrication has become inevitable. Modern System on chip (SoC) is complex process. Modern SoC‟s can be designed time effectively and cost effectively with the help of third party Intellectual Property (IP) core vendors. Various processors cores (like ARM, Power PC), communication controllers (CAN, Zigbee) and control cores (PWM, Analog comparator) will get incorporated into SoC‟s, which are supplied by different vendors. The original SoC manufacturers are IP integrators, targeting a particular application. In this process, various issues like IP protection, IP rights and problem of malicious IP‟s will arise. Recent addition in this list is Hardware Trojans (HT). HT‟s can be included by rogue designer in design house or at overseas fabrication factories. The objective of these HT‟s includes manipulating the functionality of the chip, leaking confidential information and destroying the system. HT‟s included in the design phase must be weeded out during verification phase. Still now, there is no concrete method or golden rule in the existing verification framework to detect the HT‟s. Various verification metrics like code coverage, functional coverage and verification methodologies like OVM or UVM will be helpful in detecting HT‟s. Formal verification is also useful. A comprehensive framework using all verification metrics is very much required to detect HT‟s. We will address this issue in our thesis. Secondly, static timing analysis (STA) and power analysis (PA) can be used to detect HT‟s included at both design phase and also in fabrication. In our proposed framework, we will incorporate verification metrics, formal verification, STA and PA to detect HT‟s. In this report, we apply DFT techniques and standard verification metrics to detect the hardware Trojans. The microprocessors and cryptographic designs are most vulnerable for hardware Trojan attacks. The Advanced Encryption Standard (AES) and RSA Trojan benchmarks from Trust Hub are used to verify the existing test principles like stuck at fault (SAF), path delay faults (PDF) are capable of detecting Trojans in Benchmarks. Results and analysis is presented in this report. Also Novel Trojan Benchmarks designs were proposed to eliminate the existing weaknesses in AES Benchmarks.

Item Type:Thesis (MTech)
Uncontrolled Keywords:Intellectual Property, System-on-Chip, Advanced Encryption Standard, Stuck-at-Fault, Path-Delay-Fault, Hardware Trojan
Subjects:Engineering and Technology > Electronics and Communication Engineering > Cryptography
Engineering and Technology > Electronics and Communication Engineering > VLSI
Divisions: Engineering and Technology > Department of Electronics and Communication Engineering
ID Code:7741
Deposited By:Mr. Sanat Kumar Behera
Deposited On:29 May 2016 12:02
Last Modified:29 May 2016 12:02
Supervisor(s):Mahapatra, K K

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