HDL Implementation of OMP Based Compressed Sampled Reconstruction Algorithm

Abstract

Nearly all signal acquisition techniques follow the much celebrated Shannon’s sampling theorem which specifies that the sampling rate of the signal must be at least two times the highest frequency present in the signal. The sampled data is then compressed to make it efficient for storage and transmission. Conventional approach to sampling is expensive in terms of data storage and transmission due to the large number of samples generated. Some cases increasing sampling rate is also very expensive like high speed ADCs, imaging systems, etc. It is also inefficient since lot of the data produced is redundant in nature since most naturally occurring signals are sparse in nature. Compressive sensing addresses these inefficiencies by directly acquiring a compressed signal representation without going through the intermediate stage of acquiring all samples. The sampled data can be reconstructed using computationally intensive algorithm. CS is also superior to conventional approaches in the following regard that the CS performs the time consuming processes at the recovery end rather than the sensing end. Reconstruction algorithms are complex and implementation of these algorithms in software is extremely slow and power consuming due to the reason that it is based on several layer of abstraction and shared resources between multiple processes. On the other hand hardware implementation takes advantage of hardware parallelism, custom datapath creation ability and dedicated hardware for each task. The hardware implementation in the project will be utilizing the OMP algorithm due to its less complexity and faster solution time. The algorithm will be implemented using VHDL. The objective of the project will be to implement the OMP algorithm using optimal resources so as to reduce the reconstruction time without compromising with accuracy intended.