Design of Low2power Full Adder Using Different Hybrid Logic Styles

Abstract

Full adder is a basic and most important digital component. To improve the full adder architecture many improvements has been made. Here we present Hybrid CMOS full adder, ULP (Ultra low power) full adder and two new design full adders that is Hybrid logic style and GDI(gate diffusion input ) Structure. These two new full adders consists less number of transistors (i.e.12 transistors) compared to previously designed full adders. The motive of adder cell is to provide high speed, low power consumption and also to give high voltage swing. The Hybrid CMOS logic full adder and ULP full adder uses CPL logic, transmission gates and Static CMOS logic styles. New hybrid full adder uses semi XOR-XNOR gates and GDI-MUX full adder with a new design which eliminates the use XOR-XNOR gates and also uses GDI (gate diffusion input) cell with 12 transistors provides low power, high speed and also full voltage swing. Theses design are implemented in Cadence virtuoso software using 90nm technology GPDK tool kit and comparison of Power, Delay and Power delay product (PDP) is done.