Low Power Dynamic Comparator Design Using Variable Resistor

Abstract

In today's reality, where claim for versatile battery functioned gadgets is expanding, a noteworthy plunge is given in the direction of low power approaches for rapid applications. To reduce the feature size is the cause to reduce the power. The comparator is one of the most versatile circuits in analog circuit design. It serves as an input stage of most of the ADCs. The comparator has noteworthy effect on the execution of the objective application which depends on the architecture and form of it. In this thesis, a clock based comparator is analysed in terms of average power dissipation, delay power-delay product (PDP). An investigation of modified double tail dynamic comparator has been carried out using post layout simulations. Based on the analytical expressions, a new comparator circuit that consumes less power has been proposed. Simple modification has been done by adding MOS transistor that works as voltage variable resistor (MOSFET in triode region) to reduce power. The delay of the proposed circuit is also improved as the voltage variable resistor increases the differential voltage in pre amplifier stage. Post layout simulation of the design in 90nm CMOS technology is presented. The average power dissipations of the proposed comparator at two different supply voltages which is 0.6 and 1.2 V are 0.842 µW and 2.68 µW respectively. The clock frequency at which circuit gives proper output of the proposed circuit goes up to 1.33GHz and 1GHz at supply voltages of 1.2V and 0.6V.