8 Bit Segmented Current Steering DAC

Banik, Nabin (2016) 8 Bit Segmented Current Steering DAC. MTech thesis.

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Abstract

This present study describes the designing of current steering DAC, which is an important block in many VLSI chips. A segmented architecture has been described in this study. The DAC has been designed to convert 8 bit digital input code to its analog counterpart. The segmentation is done is such way that the 2 bit is binary and 6 bit is unary architecture. The input binary bits are fed to an input data register to synchronize the input bits with respect to the system clock. Then the lower two bits are given to the binary block and upper 6 are fed to the unary block. Thermometric decoder is being introduced to the unary block as the unary architecture needs thermometric codes. Instead of 6 to 64 decoder two 3 to 8 row and column decoders are used. The reason is to reduce the decoder size as large decoder will produce large delay. To get 64 signals out of that 16 row and column decoders output a local decoder matrix along with a final retiming latch is introduced. The final retiming latch will provide control signal to the current switches. There will be current sources of 3 value, I and 2I for first two binary architecture bits and 4I for the rest unary architecture bits. A current reference circuit is designed in order to bias the current sources. A delay block is introduced to match the timing of unary and binary blocks. Finally, the transient output for RAMP input and SINE input carried out. The INL and DNL plot are also drawn.

Item Type:Thesis (MTech)
Uncontrolled Keywords:Unary;Binary;Segmented;Thermometric Decoder;Local Decoder.
Subjects:Engineering and Technology > Electronics and Communication Engineering > VLSI
Divisions: Engineering and Technology > Department of Electronics and Communication Engineering
ID Code:8069
Deposited By:Mr. Sanat Kumar Behera
Deposited On:30 Jul 2017 17:29
Last Modified:30 Jul 2017 17:29
Supervisor(s):Sarkar, Santanu

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