Power Integrity Analysis For Jitter Characterization

Abstract

Continuous improvements in the VLSI domain have enabled the integration of billions of transistors on the same die operating at frequencies in the gigahertz range. These advancements have brought upon the era of system-on-chip (SoC). Traditionally, analog ICs has been prone to device noise while digital ICs have typically not been the prime concern being considered as relatively immune to noise. With faster transition times and denser integration, the scenario wherein digital ICs were considered to be immune to noise has changed significantly. Drastic changes in the physical design of an IC and increase in the operating frequencies has immensely changed the classical understanding of noise in the new age complex ICs. Switching noise specifically has become a dominating criteria for high performance digital and mixed signal ICs. Voltage variations on the power/ground nodes of a circuit is a type of switching noise affecting digital and mixed-signal ICs. Therefore, power integrity (PI) has become a critical challenge that must be addressed at the system level considering the parasitic effects of package and board. In this work, a die, package and board modeling and co-simulation methodology is presented which can be easily integrated into a standard VLSI design flow. This methodology involves breaking down the system in multiple components and generating models for each component to observe individual performance. System level response can be seen by combining them together. This approach has been successfully exploited to guarantee the power integrity on an industrial design. This approach becomes successful in providing a systematic and a widely reusable method to estimate integrity issues before fabrication, thus exhibiting its worthiness as a design step in avoiding failures and re-spins.