Novel Techniques for SRAM Based Memory Performance Enhancement

Abstract

Digital computation has penetrated diversity of applications such as audio visual communication, biomedical applications, industrial application, defense application, entertainment industries, remote sensing and control etc. Electrical systems having digital computing capability have become an integral part of daily life. This puts a thrust to design the systems with utmost portability. Portability of an electronic system not only depends on the physical size of computation blocks embedded inside it but also on the energy consumption by it. Thus, reduction of size of computing block along with the reduction of energy consumption has become prime necessity. As per ITRS (International Technology Roadmap for Semiconductors 2011, http://www.itrs.net/Common/2011ITRS/Home2011.htm.) the SRAM occupies more than 70% area of the SoC. Hence, the performance of the SRAM predominates the overall performance of the SoC. The basic operation of SRAM cells is simple and well-known. But the diversity among various applications requires different objectives to be achieved based on the field of application. Energy consumption, speed of operation, cell stability and area occupancy are the most important aspects of SRAM which need to be optimized for various applications. These parameters are commonly interdependent among each other. Thus improving one performance can potentially degrade the other one. Hence the objective which is most important for a particular application may be enhanced with compromising another performance index which may not be so critical for that particular application. In this thesis we have focused on various techniques to improve the performance of SRAM based memory.