Agarwal, Nitesh (2017) Design and Implementation of UART on FPGA. MTech thesis.
|PDF (Fulltext is restricted upto 18.01.2020) |
Restricted to Repository staff only
A UART (Universal Asynchronous Receiver Transmitter) is typically a piece of hardware on microcontrollers or computers that changes data between serial and parallel forms. It is used for serial communication of data and encompasses a transmitter (which is essentially a parallel to serial converter), a receiver (which is essentially a serial to parallel converter) and both are clocked separately. UART is often connected to the bus of the device that carries parallel data. When a data byte is written to the transmitting data register of a UART by the data-bus, the UART will convert it to serial form starts to transmit the data on the serial line. UARTs are frequently utilized with communication standards like RS-485 or RS-232. Data format and transmission speeds (known as baud rate) are configurable in the UARTs and the electric signaling levels and techniques are commonly taken care of by the driver circuits that is external to the UART. UARTs can work in both Full duplex and Half duplex modes of communication.
In this thesis, design to Semi-custom layout is performed for the UART (both in Full duplex and Half duplex mode). Verilog HDL (Hardware Description Language) is used here for Register Transfer Level (RTL) coding. Simulation of RTL code is done using Synopsys VCS and cadence ncsim for both the designs. Synthesized netlist for Half-duplex design is created by using Cadence RTL compiler, whereas for Full-duplex design it is created by using Synopsys Design Vision. Finally, for Place and Route SoC Encounter tool from Cadence is used. SCL 180nm library is used for implementing the design.
Half-duplex UART design is verified on FPGA board (Xilinx, Spartan 3E, XC3S500E) in the loop-back mode. In Half-duplex, two UARTs are designed and dumped on the single FPGA board, after that data is transmitted serially from UART1 to UART2 and vice-versa, whereas parallel data that is to be transmitted is generated by the LFSRs. Full-duplex UART design is also verified using the FPGA board (Xilinx, Spartan 3E, XC3S500E).
In Full-duplex, two FPGA boards are used to check the functionality and feasibility of the design. UART design is then dumped on both the FPGA boards, then the data is exchanged serially between both the boards using the RS-232 cable, whereas the parallel data that is to be transmitted is generated by the LFSRs when the earlier byte is successfully transmitted.
|Item Type:||Thesis (MTech)|
|Uncontrolled Keywords:||UART; Transmitter; Receiver; Baud Rate; Simulation; Synthesis; FPGA; Layout|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > VLSI|
|Divisions:||Engineering and Technology > Department of Electronics and Communication Engineering|
|Deposited By:||Mr. Kshirod Das|
|Deposited On:||16 Mar 2018 11:54|
|Last Modified:||16 Mar 2018 11:54|
|Supervisor(s):||Mahapatra, Kamala kanta|
Repository Staff Only: item control page