Kumar, Abhishek (2017) Low-Power Network on chip Architecture. MTech thesis.
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Due to rapid development in the field of technology, we are able to integrate many devices on a single chip. So the communication between these devices becomes noticeably indispensable.The network on chip (NoC) is a technology which is used for such communicate on. The fundamental component of a NoC is a router. Be that as it may, in NoC design, there is power, area, and performance trade-off in topology, buffer sizes, routing algorithms and flow control mechanisms. For the NoC, the architecture of router must be an efficient one for balancing all things in the NoC and it should have lower latency and higher throughput. We implemented 5x5 NoC
architectures, and its buffer, switch control, router which are synthesis through vhdl language. A parametric analysis for different NoC was done using different for evaluating for the maximum frequency.To design the above design we use VERILOG HDL and VHDL language, the simulation and Synthesis done through “XILINX ISE 14.2”tool. The simulation results of shows the validation of functionality of the designs and the synthesis result shows the clear picture of resource. From the Parametric based evaluation of the different NoCs, the 5X5NoC archivedthe minimum of 435.374Mbps under the clock frequency off 100 MHz and the maximum of latency of41.5 clock cycles.
Through clock gating process on the NoC5x5, we saved significant die area equal to 6.13% as well as power saving of 47.82%, since it removed large numbers of muxes and replaced them with clock gating logic.
|Item Type:||Thesis (MTech)|
|Uncontrolled Keywords:||Network on chip (NoC); Router; Mesh; FBW; FBD; VC|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > VLSI|
|Divisions:||Engineering and Technology > Department of Electronics and Communication Engineering|
|Deposited By:||Mr. Kshirod Das|
|Deposited On:||27 Mar 2018 16:02|
|Last Modified:||27 Mar 2018 16:02|
|Supervisor(s):||Swain, Ayas Kanta|
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