SNM Analysis & SRAM Based Memory Design

Abstract

In digital systems memory arrays are forming an integral building block. There are various aspects that need to be known to begin with the design of SRAM based memory and are vital for design of many other digital circuits. The integrated circuit that is known to consume majority of space is memory. Design considerations for SRAM consists of factors like increasing speed and minimizing the area being consumed. The stability of SRAM cells is a major concern and is reduced due to technology being scaled. In SRAM design, accurately estimating the stability issues of SRAM storage cell is thus extremely important. Traditional 6T SRAM cell is designed using CMOS process technology UMC 65nm. Comparative analysis for bit cell topologies is done for the stability metrics. In this thesis, work that has been presented consists of SRAM cell stability analysis in terms of noise margin. Empirical analysis is done so as to understand effect of various parameters on SNM of the bit cell designed namely RSNM, HSNM, WNM. Hence, objective analysis of various parameters affecting SNM of 6T SRAM cell has been presented. The effect of parameters like cell ratio, pull-up ratio, temperature, supply voltage, threshold voltage and process corner variations on the SNM of bit cell is studied and analysed. Design of 256 word 32-bit SRAM based register file has been presented in this thesis using SCL 180nm which is operating at a frequency of 500MHz. All the peripherals like pre-charge circuit, decoder, word line driver, sense amplifier, column multiplexer and write driver are designed and layouts of all the peripherals mentioned above have been also drawn. The 6T SRAM cell is designed with operating frequency of 2 GHz and stability analysis is performed for single SRAM cell. Symmetrical layout of the 6T SRAM cell is drawn, such that same contacts can be shared by two adjacent cells resulting in reduction in the layout area of cell.