Mudiyala, Sandeepthi (2017) Programmable Logic Circuit for Face Detection. MTech thesis.
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Face detection is increasing its importance in several applications of Image processing such as in human-computer interfaces, intelligent robots, surveillance and security applications and in consumer products such as web-cams in PCs, digital cameras and Smart phones. The main constraints of Face detection are its speed and accuracy. Face detection algorithm in software has a high response time i.e in the order of 100msec as it executes sequentially. For certain applications like in consumer products, the software solution response time is adequate. Whereas in security applications, it needs very less response time in the order of 10msec or less.
The basic Viola-Jones algorithm which uses haar features can be used to detect faces which is tested in MATLAB R2015 platform and gives the execution time as 0.85sec. Hence, it cannot be used for all real-time applications due to its latency. Haar-classifier function in Viola-Jones algorithm consumes 93% of the total execution time.As a result of using parallel architecture for implementing these tasks, the total performance of many applications can be enhanced than the software solution. This report explores a parallel implementation of face detection algorithm on the Programmable logic circuit. Here, an approach to parallelize the Haar-classifier based Viola-Jones face detection algorithm is studied, analyzed and a programmable logic circuit is designed and simulated in Vivado design suite which yields the frame rate of 17fps.
|Item Type:||Thesis (MTech)|
|Uncontrolled Keywords:||Face detection; Viola-Jones algorithm; Haar-classifier; Parallel processing; FPGA|
|Subjects:||Engineering and Technology > Electrical Engineering > Image Processing|
|Divisions:||Engineering and Technology > Department of Electrical Engineering|
|Deposited By:||Mr. Kshirod Das|
|Deposited On:||19 Apr 2018 17:31|
|Last Modified:||19 Apr 2018 17:31|
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