Khandagale, Sachin (2016) Design of 10-bit 500 MSPS Segmented Current Steering DAC for Telecommunication Applications. MTech thesis.
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This work describes the design of 10 bit segmented current steering (CS) digital to analog converter (DAC) with 60 percent segmentation which uses Chinese abacus technique to improve both static and dynamic performances. Chinese abacus DAC is simple, occupies less area and shows better linearity compared to binary DAC. In conventional segmented CS architecture, the MSB is implemented in unary and LSB is implemented in binary. In the proposed design the binary section of segmented architecture is replaced by Chinese abacus sub-DAC to minimize noise i.e., glitch energy and to improve the spurious performance. The modified CS architecture is segmented as 6+4, to achieve optimum performance and to minimise area, where 6 most significant bits (MSBs) are realized using a unary sub-DAC and 4 least significant bits (LSBs) are implemented in Chinese abacus technique. This proposed DAC consists of only three different types of current sources. All the current sources have been biased using temperature and supply independent current reference. The proposed architecture is designed and simulated in 0.18 μm CMOS technology at 1.8 V power supply at 27 °C temperature. To verify the claims, we have designed 8-bit segmented DAC (4+4) using Chinese abacus technique. The results obtained with this proposed architecture for 8-bit DAC are more satisfactory than other architectures in most performance parameters. This has given strong foundation to go for 10-bit implementation using the same technique. The proposed DAC will be used for high speed telecommunication purposes, so requirement is that it should have better performance for high speed digital to analog conversion. It is seen that at high frequency the spectral performance of DAC degrades rapidly due to the increase in parasitics. Our aim in this work is to improve static as well dynamic performance by optimum design of current sources. To make it robust in wide range of temperature environments, in our design an optimum current reference is designed to bias current cells of sub-DACs. The glitches at output of the DAC directly or indirectly degrade the other performance parameters, so it is needed to have less number of glitches at the output. The glitch is short span high magnitude output mostly occur due to mid-code transition. In unary architecture requirement of physical area on chip is more, as well as it has high power dissipation, but has advantage of good differential nonlinearity (DNL). To enhance performance of DAC in all respects, segmented architecture is used that will combine advantages of both individual architectures. It is suggested by previously reported works to use a current steering architecture for high speed data conversion. All schematic level designs are done in virtuoso schematic design tool of Cadence IC 6.1.6 and executed in spectre simulator. Layout is done in virtuoso layout design environment while post layout design verifications like DRC (Design rule check) and LVS (layout versus Schematic) are done in Assura tools. The technology used for design is UMC 180 nm CMOS process with six metal layers. The proposed 10-bit DAC achieves maximum DNL and integral nonlinearity (INL) of 0.28 LSB and 0.19 LSB, respectively. The maximum spurious free dynamic rage (SFDR) achieved is 65.02 dB.
|Item Type:||Thesis (MTech)|
|Uncontrolled Keywords:||Segmented DAC; DNL; INL; SFDR; Glitch|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > VLSI|
|Divisions:||Engineering and Technology > Department of Electronics and Communication Engineering|
|Deposited By:||Mr. Sanat Kumar Behera|
|Deposited On:||06 May 2018 16:36|
|Last Modified:||06 May 2018 16:36|
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