Design of 10-Bit Segmented DAC

Mohapatra, Saikat (2016) Design of 10-Bit Segmented DAC. MTech thesis.

[img]PDF (Fulltext is restricted upto 05.05.2020)
Restricted to Repository staff only



Digital to analog converter (DAC) acts like a path between DSP chips and power amplifiers used for transmission of analog signal. Every communication system prefers the advantage of bandwidth, so data converters are the pipeline for every communication system. This paper describes the necessity, architecture and design techniques of a current steering segmented DAC with favorable current sources to maintain the balance between accuracy and chip area consumption. Using CMOS 180 nm technology, a product of National Semiconductor, the proposed DAC was designed.
The 10-bit DAC was divided to two parts of five bits where 5 MSB bits are implemented as unary DAC and other 5 LSB bits are implemented as binary DAC. The unary DAC plays an important role to improve the total linearity of the converter. The binary part reduces the consumption area on chip by sacrificing the linearity. To achieve improved static in addition with dynamic linearity the special care was took place during the design of current sources. The large size of the current sources may cause the parasitic increment which reduces the performance of the DAC at high frequency. The DNL and INL measured for this DAC is 0.018 LSB and 0.03 LSB respectively at 500 MSPS sampling and 1.8 V power supply.

Item Type:Thesis (MTech)
Uncontrolled Keywords:Unary DAC; Binary DAC; Segmented DAC; Current steering DAC; Parasitic; DNL; INL
Subjects:Engineering and Technology > Electronics and Communication Engineering > VLSI
Divisions: Engineering and Technology > Department of Electronics and Communication Engineering
ID Code:9141
Deposited By:Mr. Sanat Kumar Behera
Deposited On:06 May 2018 16:29
Last Modified:06 May 2018 16:29
Supervisor(s):Sarkar, Santanu

Repository Staff Only: item control page