Ranjan, Raju (2016) Design of Low Power Operational Amplifier and Digital Latch Circuits Using Power Efficient Charge Steering Technique. MTech thesis.
|PDF (Full text is restricted upto 04.04.2020) |
Restricted to Repository staff only
Power consumption is a burning issue in the present world. The on-going research is on its course to discover power efficient design techniques. The reduction in power dissipation can be done by transformation into discrete-time charge-steering circuits from continuous-time current-steering circuits. An effective technique to reduce power dissipation in high-speed circuits could be charge steering. Exploitation of this technique can be done in the design of both analog and semi-analog circuits like op-amp, latches and clock-data recovery (CDR) circuits. The point of discussion of this paper is the design techniques of charge steering circuits like op-amps and latches. Both 1st stage and 2nd stage op-amp circuits and different type of latches in a single stage and cascade forms are designed. In order to show the improvements, conventional design techniques like current-mode logic circuits (CML) are compared with the power and performances of the charge steering circuits. The results offer visible proof of the reduction in power dissipation of the op-amp by approximately 87 percent with better gain. UMC’s (United Micro-electronics Corporation) 180 nm CMOS technology have been used to design all circuits.
|Item Type:||Thesis (MTech)|
|Uncontrolled Keywords:||Charge-Steering; Power Dissipation; Operational Amplifier (OP-Amp); Common Mode Logic (CML)|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > VLSI|
|Divisions:||Engineering and Technology > Department of Electronics and Communication Engineering|
|Deposited By:||Mr. Sanat Kumar Behera|
|Deposited On:||05 Apr 2018 18:21|
|Last Modified:||05 Apr 2018 18:21|
Repository Staff Only: item control page