Designing of a MDAC Stage for 10-bit 100 MSPS Pipeline ADC

Abstract

As technology develops, there is an increasing need for high-performance digital signal processors. This, in turn, demands high-speed and high-performance data converters. This thesis describes the design and implementation of Switched Capacitor based Multiplying Digital-to- Analog Converter (SC-MDAC) used in the 1.5-bit pipeline stage of a pipeline ADC, and the MDAC should meet requirements of a 100 MSPS 10-bit pipeline ADC with 1.8V supply voltage. To meet the requirements such as high speed and high resolution, a bulk switching transmission and an operational amplifier with high gain and high unity gain bandwidth are designed. A gain boosted folded cascode architecture is used in the design of amplifier. To attain maximum performance a careful optimization is conducted in between power and speed. The design is implemented in the UMC 180 nm CMOS technology process with 1.44 mW power consumption. The simulation results in Spectre illustrate that the designed MDAC circuit could reach the fixed goal and the residue signal of MDAC could set up completely in the specified time of 4.7 ns