Development of a Generic Verification Environment for Behavioral Models of AMS IPs Using SV-UVM

Abstract

In the design process of a chip, 30% of design time is dedicated for designing and 70% of time is spent for verification. This shows the importance of verification in the design flow. Verification has gained predominant importance in the last decade, many new methodologies are developed for rigorous and robust verification of the designs like VMM, URM, OVM, AVM and UVM. For successful tapeout of a chip the steps followed know the specification, make the behavioral model for the design and convert it to a RTL description with the help of synthesis tools. This is the basic building block of any RTL to GDS flow. But all designs are not synthesizable, for example analog blocks are not synthesizable. Hence there will not be any RTL description for analog blocks.
For analog models only transistor level netlist will be provided for complete verification of Soc. SPICE tools are used for simulating these models, are accurate but the takes huge time. Hence behavioral models are written for analog models so that verification for SoC will be done in less amount of time. Finally equivalence checking will be performed between behavioral description and transistor level netlist.
Generic Verification environment is developed using Universal Verification Methodology to reduce the verification time which in turn reduces the design time. It is developed in such a way that it can handle any number of pins and any configuration. So the design time will be reduced, throughput increases and time to market is met very soon.