FPGA Based Low Cost JTOL & BER Platform for Receiver Characterization of A High Speed Serial Link PHY

Abstract

In the field of VLSI there has always been three main factors of concern i.e. Cost, Area, Speed. In High Speed applications with the increase in data rates there is always an issue surrounding the Signal Integrity of the signal being transmitted and received across the receiver side. At high frequencies there are possibilities of the data being transferred is not a pure signal but a jittered one with some Error Rate. In the industries Receiver Characterization is based on loopback methodology which involves the utilization of some High end Instruments which is costly and also Time to market is more for it. Today, FPGAs have had an increased use of dedicated communication interface links. Bit error rate (BER) estimation plays a critical role in evaluating performance of any digital design system.BER testing is a very time consuming process when it comes to software simulations and instrumentation. Hardware platform for BER evaluation is costly. To meet these challenges, this thesis presents an approach for BER estimation in FPGAs, wherein Jitter is injected into the data stream internally in FPGA through its Delay Chain mechanism.USB 2.0 PHY is the device under test at the receiver side. We present through case studies, Simulations, Hardware implementation in FPGA showcases that this BER estimation methodology possesses benefits with regards to Speed, Cost and Time to Market.