Low Power Parallel Self Timed Adder

Abstract

The performance of the system mainly depends on the individual modules integrated in the system, if they designed with low power and high speed then the system performance and the power required to complete each operation will be optimum. The power required to complete one operation is also should be minimum, so that it will be reliable and will work for long time.Binary adders of any computing system can effect the throughput of the system.Recursive Parallel Self-Timed Adder is an asynchronous single railed adder, works in parallel manner, so it doesn’t require any extra circuitry for carry generation and it doesn’t require to wait for previous state results. The multi-bit operation can be done by recursive formulation. It doesn’t have any practical limitations of high FAN OUT problems but it have High FAN IN, which is not avoidable in asynchronous logic circuits. The design has implemented with GDI technique, which has good design metrics when compare to the conventional CMOS implementation, in terms of speed and power. The schematic and layout of design has been done by using GPDK 90nm and compared its results with existing designs. The results shows that the proposed adder design has superiority in terms of MOS transistors count, power consumption and the speed over the existing asynchronous adders. The average power dissipation of the proposed design for different inputs is i.e. best case, average case and worst case with 1.2 V Vdd are 25.78 uW, 26.65 uW and 29.412 uW respectively. The over all improvement in the proposed design i.e. Low Power Parallel Self timed Adder is 34% decrease in transistor count, 32 % in delay improvement and 27 % power improvement in power consumption