Talukdar, Dipankar (2016) Modeling and Simulation for Direct Gate Tunneling and Drain Current of Recessed Source/Drain SOI MOSFET. MTech thesis.
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The scaling of transistor has beenathe main thrust for innovation progressions inathe electronics semiconductor industry in the course of the most recent couple of decades. Keepingi ini mind the end goal to moderate short channeli effects (SCEs), the gate insulatori thicknessi andi source/drain junction depthi have beeni scaled down along with the channel length. As of late, notwithstanding, gate insulatori thicknessi scaling has impeded, as prove by the way that a effective oxidei thickness (EOT) .of 1 nmi hasi been utilized for as far back as 2-3 eras of CMOS innovation. Thoughi critical advancement has.been.done.in the improvement of high-permittivity. (high-κ) i dielectrici materials and metali gate innovation as of late, it will be hard proportional EOT well underneath 1 nm. This i makes source/drain junction depth i scaling considerably additionally squeezing for proceeded with transistori scaling. Moreover, asi thei measurements of MOSFETsi are downsized, the contact i resistance, leakage current problem progressively restricts transistor execution. This is on the grounds that the on-state resistance of a i MOSFET drops with i transistor scaling, while i contact resistance increments with contact territory scaling. Contact resistance increases rapidly. So to minimize the SCEs as well as to increase the drain current.a i new i device called recessed i source/drain. (Re S/D) SOI MOSFET i come into picture. And it is very important to express mathematically the amount of direct gate tunneling current of the device for better understanding and easy to implement in circuits.
Firstly, an analytical i model for direct i gate i tunneling current of Recessed i Source/Drain Siliconi Oni Insulator (Re S/D SOI) .MOSFET hasi been proposed. The surface potential of the device has been modeled byi solving.the 2D poisson’si equationi assuming.a parabolic profile of surface potential in.the transverse direction of the channel. From the surface potential model we can calculate for minimum surface potential, which is then used.for the.calculation of direct gate i tunnelingi current. .The proposed model is then verified by varying different parameters like gate insulator thickness, channel doping concentration, drain.to.source voltage, for different gate dielectric materials.
Lastly, we propose an analytical model to describe the drain current dependency on applied gate i voltage.and drain i voltage.of the device. For that, the charge in the channel region has been formulated and it has found that there is a linear dependency between the charge and applied voltages and surface potential of the device. It is found from the model that the proposed device model does not match with the conventional square law of on current for conventional bulk MOSFET. The proposed model is then verified by varying different parameters like applied gate voltage, channel thickness and source drain extension into the buried insulator region. To validate both the models we do the 2D simulation of the device by using the ATLAS tool from Silvaco.
|Item Type:||Thesis (MTech)|
|Uncontrolled Keywords:||Re S/D SOI.MOSFET; High K dielectric material; direct gate tunneling current; drain current|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > VLSI|
|Divisions:||Engineering and Technology > Department of Electronics and Communication Engineering|
|Deposited By:||Mr. Sanat Kumar Behera|
|Deposited On:||05 May 2018 13:39|
|Last Modified:||05 May 2018 13:39|
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