Modeling Power, Performance and Area Profile for Processor

Kumar, Vipin (2016) Modeling Power, Performance and Area Profile for Processor. MTech thesis.

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The continuous shrinking size of transistors have resulted in faster devices and there is never ending demand for more speed and low power devices. The major driver for these demands is the hand held devices, the processing power of these devices are tremendous and they are capable of performing millions of calculation per second. This market drives industries to come up with better technology and design. So it is very important to have good planning and analysis for the design to achieve the required performance to survive in the market.
Industries focus on worst case design strategy which results in area over-dimensioning to achieve the target since it involves extreme process corner conditions which rarely occur in real scenarios. A comparison between body bias design (BBD) strategy and worst case design (WCD) strategy for 28nm FDSOI technology is presented which shows the performance gain without area over-dimensioning. It is suggested that a nominal design strategy should be followed i.e. in between WCD and BBD strategy. Therefore maintaining the trade-off between power consumption, speed and area.
The well-established industrial practice to know the performance of the processor involves extensive synthesis trials. This practice is somewhat like trial an error method as the synthesis runs are launched for different frequencies on the basis of experience and intelligent guess keeping vendors specification in consideration. In this work a mathematical model is presented which aids fast reconstruction of area-clock period trade-off curve for the design in minimum number of trials, hence reducing the time and effort exponentially. The model is validated on an ARM core on 28nm low power CMOS technology. The results shows frequency increase of 51% for regular Vth (RVT) and 39% for low Vth (LVT) transistors, area reduction of 7% for both LVT & RVT, dynamic power reduction is 24% for RVT and 19% for LVT at 0.7V VDD and 0.6V forward body bias and it has been observed that these advantages reduces for higher voltages.

Item Type:Thesis (MTech)
Uncontrolled Keywords:RVT; LVT; WCD; BBD; FBB; Performance per unit area (PPA); LMA
Subjects:Engineering and Technology > Electronics and Communication Engineering > VLSI
Divisions: Engineering and Technology > Department of Electronics and Communication Engineering
ID Code:9235
Deposited By:Mr. Sanat Kumar Behera
Deposited On:05 May 2018 12:09
Last Modified:05 May 2018 12:09
Supervisor(s):Swain, Ayas Kanta

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