Babu, Kunda Rajesh (2016) Network-on-Chip Design: An Architectural Exploration. MTech thesis.
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With the technological advancements a large number of devices can be integrated into a single chip. So the communication between these devices becomes vital. The network on chip (NoC) is a technology2used for such communication. A router is the fundamental component of a NoC. However, NoC designs have many power, area, and performance trade-offs in topology, buffer sizes, routing algorithms and flow control mechanisms. So by balancing all tradeoffs the architecture of router must be an efficient one with a lower latency and higher throughput.
In this dissertation we designed router blocks such as Arbiters, Allocators and crossbar switch, routing algorithms such as XY, balanced and adaptive and look ahead routing algorithms for the Mesh and Torus and we designed a 5 port credit based router architecture. With the designed router we implemented 2X2 and 3X3 NoC architectures and a parametric analysis for different NoC using different for evaluating the FPGA resources and maximum frequency.
The above all designs are designed in VERILOG HDL and VHDL language, the simulation and Synthesis carried out using XILINX ISE 14.2 tool. The simulation results of shows the validation of functionality of the designs and the synthesis results shows the clear picture of resource utilization in FPGA.
From the Parametric based evaluation of the different NoCs, The 3X3 NoC is archiving the minimum of 308.433 Mbps under the clock frequency off 100 MHz and the maximum of latency is 41.5 clock cycles.
|Item Type:||Thesis (MTech)|
|Uncontrolled Keywords:||Network on chip (NoC); Router; Mesh; FBW; FBD; VC|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > VLSI|
|Divisions:||Engineering and Technology > Department of Electronics and Communication Engineering|
|Deposited By:||Mr. Sanat Kumar Behera|
|Deposited On:||30 Apr 2018 17:58|
|Last Modified:||30 Apr 2018 17:58|
|Supervisor(s):||Swain, Ayas Kanta|
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