Das, Rakesh Kumar (2016) On Chip Process Monitoring Sensor Design and Validation. MTech thesis.
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In this proposed some back end and front end process monitoring sensors are made, which will give the information about the statistical process variation, which a chip encountered. Statistical process variations are the variations which incurred due to the lack of control over the physical process parameters; such as controlling the thickness of the gate oxide, random dopant fluctuation, Improper etching, line edge roughness etc
Due to the statistical process variation, there is maximum possibilities of failure of your design and less yield. This process can’t be removed but they can be reduced by improving the fabrication process. But due physical limitation over controlling the statistical parameter, an alternate approach should be adapted. Based on the transistor and interconnect properties and their dependencies on external process parameters, these variation can be compensated. Hence a proper and accurate method to be chosen to know the process parameters after fabrication, so that an appropriate compensation technique can be applied.
In this work the process variations are detected by ring oscillator method. In CMOS technology n-MOS and p-MOS are the main devices. For monitoring their process two separated ring oscillator are made which are sensitive to n-MOS and p-MOS transistor respectively. These two sensors are made for Body Bias process compensation technique .For applying the adaptive voltage scaling one Critical path replica sensor made with the standard cells available, which will give the cumulative process effect of n-MOS and p-MOS. For Backend Process monitoring purpose three ring oscillators are made, one for getting the single inverter delay and two ring oscillators for lateral and vertical coupling effect.
The above mentioned sensors are giving proper and more accurate results both at CAD level and in silicon level.
|Item Type:||Thesis (MTech)|
|Uncontrolled Keywords:||Statistical Process Variation; Process Corner; fabrication steps; Ring Oscillator; gate delay|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > VLSI|
|Divisions:||Engineering and Technology > Department of Electronics and Communication Engineering|
|Deposited By:||Mr. Sanat Kumar Behera|
|Deposited On:||30 Apr 2018 15:29|
|Last Modified:||30 Apr 2018 15:29|
|Supervisor(s):||Acharya, Debiprasad Priyabrata|
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