Pallempati, Mallikarjunarao (2016) Investigation on Spacer Engineered Multigate Tunnel FETs. MTech thesis.
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In this modern era of semiconductor technology, the number of transistors per chip are increasing continuously for designing a computing system to perform innumerable of functions with tremendous speed. Thus, the electronics industry is constantly facing the challenge of miniaturization of transistors to increase the package density. Hence scaling of CMOS technology is essential in nano-electronic regime which leads to increase of static power consumption and thus conventional MOSFETs are unsuitable in this situation due to Short Channel Effects (SCEs). Hence the non-conventional devices became significant in order to achieve the requirements of ITRS.
Tunnel FET is one of the emerging devices which exhibits a very low OFF-state current in the order of 10−15A/µm due to its different current flow mechanism i.e., Bandto-Band Tunneling mechanism and thus one of the potential candidate for mitigating power crisis. Also, Tunnel FET is an energy efficient device because, it can achieve a Subthreshold Swing of sub-60mV/decade and also less sensitive towards SCEs which is a benefit over MOSFET. Due to these reasons, Tunnel FETs can replace the ongoing CMOS technology for future low power (LP) applications.
In the proposed work, an underlap silicon n-channel Tunnel Field Effect Transistor (n-TFET) i.e., symmetric single-k spacer (SSS) Double Gate N-TFET (DGTFET) is modeled to improve the performance of the device by using different spacer materials. A detailed investigation has been made on the device characteristics with the help of extensive 2-D TCAD simulations. It is demonstrated that an optimized underlap length has a significant contribution of on-state current (ION ) without deteriorating the off- state current (IOF F ) and sub-threshold swing (SS). The proposed model with different spacer materials has been extensively analyzed by using transfer characteristics, output characteristics, and analog/RF characteristics. The structure is optimized based on the comparison among various performance metrics evaluated by considering different spacer materials like SiO2 (k=3.9), Si3N4 (k=7.5), and HfO2 (k=25).
Further, temperature analysis has been performed with the help of 3-D numerical simulations by proposing Spacer Engineered Trigate Silicon-ON-Insulator (SOI) N-TFET for better Sub-threshold swing (SS) and OFF-state current (IOF F ). The proposed model can achieve a Sub-threshold swing less than 35 mV/decade at various temperatures, which is desirable for designing low power CTFET for digital circuit applications. A detailed investigation has made on the device characteristics and on various performance metrics in order to ensure its reliability for harsh temperature environment applications. Further, the Spacer Engineered Trigate SOI TFET is subjected to Heavy Ion Irradiation simulation model in order to characterize the device sensitivity towards radiation hardness point of view. A detailed investigation has been made on the Transient operation of the device by analyzing various parameters like electron density, Heavy Ion charge generation, bipolar gain and Transient Drain current. All the simulations presented in this work are done by using TCAD Sentaurus software.
|Item Type:||Thesis (MTech)|
|Uncontrolled Keywords:||Band-to-Band Tunneling; High-k spacer; Trigate TFET; Transconductance; Ambipolar; Underlap; ITRS; SCE's; Sub-threshold Swing; Silicon-on-insulator; Heavy Ion|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > VLSI|
Engineering and Technology > Electrical Engineering
|Divisions:||Engineering and Technology > Department of Electrical Engineering|
|Deposited By:||Mr. Sanat Kumar Behera|
|Deposited On:||28 Apr 2018 17:44|
|Last Modified:||28 Apr 2018 17:44|
|Supervisor(s):||Sahu, Prasanna Kumar|
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