Patel, Kiran (2016) Hardware Architecture for Image Denoising Using DWT. MTech thesis.
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The use of multiresolution technique for time-frequency analysis of signal with high directionality has found its widespread acceptance in many digital image processing applications. The demand of high speed processing and time critical tasks required a time efficient hardware implementation of such techniques. In this thesis we design and implement a flexible hardware architecture for the 2D Discrete Wavelet Transform (DWT). This architecture can be configured to perform both the forward and inverse DWT for any DWT family, using fixed-point arithmetic and without auxiliary memory. The implementation of DWT can be done using convolution and Filter Bank (FB) based approach, but we adopt Lifting scheme architecture because of its effi- cient time complexity.
The design of the architecture is done in VHDL which provides concurrent execution of statements. Initially, the DWT core is modeled using MATLAB and parameterized in VHDL. The VHDL model is then simulated using ModelSim PE Student Edition 10.4a for the implementation of Cohen-DaubechiesFeauveau CDF 5/3 versions of the DWT. We have compared its efficacy with MATLAB based implemented method. Its potential is also demonstrated to perform image denoising task under additive white Gaussian noise (AWGN). The results indicate that both the implementation of CDF 5/3 hardware and denoising produce satisfactory results but with lower time complexity. The comparison of results is demonstrated using performance measure indices.
|Item Type:||Thesis (MTech)|
|Uncontrolled Keywords:||Filter Bank; Lifting Scheme; Discrete wavelet transform; VHDL implementation|
|Subjects:||Engineering and Technology > Electrical Engineering > Image Processing|
|Divisions:||Engineering and Technology > Department of Electrical Engineering|
|Deposited By:||Mr. Sanat Kumar Behera|
|Deposited On:||06 Apr 2018 17:01|
|Last Modified:||06 Apr 2018 17:01|
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