Thermal Management in Three Dimensional Network-on-Chip Based
Systems

Abstract

Three dimensional (3D) integration technologies have a smaller footprint area of chip compared to their two dimensional (2D) counterpart. However, high on-chip temperature creates several challenges. Hotspots are created on the chip due to high temperature. It decreases system reliability and performance. It leads to increase in the cooling cost of electronic products. Work done in the thesis is an attempt to reduce peak on-chip temperature.
A thermal-aware floorplan is proposed to reduce peak on-chip temperature. In the proposed floorplan, thermally sensitive functional units are placed further apart; to reduce hotspot induced by them. The effectiveness of the proposed floorplan is evaluated with three different stacked mesh architectures – homogeneous, heterogeneous and ciliated. It is observed from the generated thermal profile that peak on-chip temperature and the number of hotspots formed are reduced to a considerable extent. To further reduce the on-chip temperature,liquid microchannels (LMC) are placed at thermally sensitive locations to the above thermal-aware floorplan. No hotspots are observed after insertion of LMCs in the generated thermal diagram. The number of LMCs required to eliminate hotspots for the considered NoC architecture is found to be five per layer. Both floorplan approach and LMC placement are application specific. The designer knows the application for which the floorplan is made.
Peak on-chip temperature can also be reduced by intelligent routing. A weighted sum approach is proposed to formulate adaptive thermal-aware routing (ATAR). The parameters considered in this approach are: (i) path length, (ii) neighbor routers temperature, (iii) link workload, and (iv) next router’s queue length. Different weights are assigned to the above parameters to find the optimal path. Three different traffic patterns with different packet injection rates are used to check the efficiency of ATAR. It is observed that ATAR gives the balanced thermal profile.
Thermal-aware hybrid routing (TAHR) is proposed to reduce hotspots on the chip. It combines two methods: (i) reactive approach, and (ii) proactive approach. The reactive approach is used when peak on-chip temperature exceeds on-chip safe temperature. Throttling is used to block the routers from sending and receiving traffic. To mitigate the performance degradation by throttling, the least throttled path is used to forward the traffic. The proactive method uses multi-objective shortest path approach using label vectors for faster packet transmission. The proposed approach is evaluated using bit-reversal, random and transpose1 traffic with varying PIR values. Above proposals intend to decrease the peak on-chip temperature and increase in performance of the chip.