Athira, A. (2018) Hardware Simulation for Face Detection. MTech thesis.
|PDF (Restricted upto 20/03/2021) |
Restricted to Repository staff only
Face detection is a primary step in many image processing and computer vision applications. Most of the instances, the image processing algorithms run on a sequential processor, thereby preventing the processing speed to increase and to meet real time constraints. On the other hand, the advent of Field Programmable Gate Arrays (FPGA) has opened an avenue to exploit the inherent parallel nature of many image processing algorithm. With the increase in parallelism, response time decreases gradually increasing the processing speed. In this work, a face detection module has been developed targeting the implementation on Programmable Logic area of a System-On-Chip (SoC). The popular Viola-Jones algorithm is converted to an equivalent hardware architecture with the help of High-level synthesis (HLS) tool. It maps the software into a reformed hardware architectures following user instructions on the target board (Xilinx Zynq SoC ZC702) hardware information. The SoC contains a dual-core ARM Cortex-A9 processor with FPGA logic fabric. We used linx SDSoC 2017.1 to generate results for C-based simulated hardware. A further step for generation of bit-stream will aid to synthesize face detection core.
|Item Type:||Thesis (MTech)|
|Uncontrolled Keywords:||Face detection; Viola Jones Algorithm; Feature Mapping; Vivado HLS; SDSoC environment; C-based Synthesis|
|Subjects:||Engineering and Technology > Electrical Engineering > Image Processing|
|Divisions:||Engineering and Technology > Department of Electrical Engineering|
|Deposited By:||IR Staff BPCL|
|Deposited On:||12 Mar 2019 14:52|
|Last Modified:||12 Mar 2019 14:52|
Repository Staff Only: item control page