Kumar, JYV Manoj (2018) Multilayer Hardware Security against Hardware Trojans in Network on Chip. MTech thesis.
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The semiconductor industry especially digital IC designing is becoming gargantuan due to automation and vast hardware requirement. Acquirement of best performing 3rdparty IP (Intellectual Property) cores are becoming inevitable to avoid sizable wastage of time and man power. The outsourcing of end product and 3rdparty Multiprocessor System on Chip (MPSoC) integration with Network on Chips (NoC) are paving a way for back door malicious Hardware Trojan insertions. The expert adversaries can find a way to insert a Trojan hardware which can be successfully bypass the code coverage and functional verification. These venomous circuits which can be present in untrusted IPs and NoCs are potential enough to steal data, cause a blockage of resources and dilute the capability of the IC design. Trojans present in the NoC are highly dangerous as they can access all inter-processor data that flows through the network. Much of the mitigation methods are concentrated in Network Interfaces (NI) and many other are IP bound methods. We propose an obfuscation-based mitigation methodology with Trojan aware routing algorithm to nullify the Trojans activities. Trojan detectable bit permutation with Error Correcting Code (ECC) is implemented to fudge and identify the HTs. The proposed method is successful in controlling Trojans adverse effects like performance distortion, denial-of-service and bit stream leakage. It is able to recover more than 75% of missing packets and improve latency by 1.25 times over the performance reducing Trojan attacks.
|Item Type:||Thesis (MTech)|
|Uncontrolled Keywords:||Multiprocessor system on chip; Hardware security; Hardware trojan; Network-on-chip; Data leakage; Denial of service; Trojan aware routing algorithm|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > VLSI|
|Divisions:||Engineering and Technology > Department of Electronics and Communication Engineering|
|Deposited By:||IR Staff BPCL|
|Deposited On:||11 Jun 2019 12:15|
|Last Modified:||11 Jun 2019 12:15|
|Supervisor(s):||Swain, Ayas Kanta|
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