Process Aware design & Optimization of Operational Transconductance Amplifier

Abstract

This work presents a novel method that is used for optimizing and provide automation in analog IC design. Rapid growth in VLSI technology leads to integration of analog and digital circuitry like pipelined ADC, Sigma delta ADC etc. Even though analog circuit constitute small portion of analog and mixed signal circuitry the design complexity and time consuming tasks make it more tedious. Here in my work I am considering optimization of Operational Transconductance Amplifier, an important part in analog design for case study. Infeasibility Driven Evolutionary Algorithm is the proposed methodology for automatic transistor sizing. This algorithm provides more efficient results compared to other gradient abased and non-gradient based optimization methods. Multiple objective functions and many nonlinear constraints can be effectively handled by this algorithm. Performance of opamp is characteristic by its dc gain, gain bandwidth power dissipation, ICMR, CMRR, slew rate etc. The important opamp parameters are considered as objective functions for the optimization problem subjected to design constraints like minimum length, width, Phase Margin, dominant pole constraints, range of bias voltages etc. The proposed approach finds the aspect ratio, compensation resistance, miller capacitance, etc. to obtain accurate opamp performance. Optimization is then extended to minimize the effect of process corner variations that arise during fabrication. The statistical deviation of process corners from nominal case is subjected to minimization and is fed to optimization engine, hence make the simulation results and testing results after fabrication to be same. This method of process aware and optimization introduce automation in analog circuit design along with increasing the yield of manufactured chips. To evaluate the proposed approach, in time and frequency domain for different process corner cases an example of OTA is considered and simulated in Cadence Virtuoso using UMC 180 nm technology. Monte Carlo analysis and post layout simulation results confirm the efficiency of IDEA optimization technique in device sizing and process aware design in analog circuits.