Securing Test Wrapper for SoC using Physical Unclonable Function

Seth, Saurabh (2018) Securing Test Wrapper for SoC using Physical Unclonable Function. MTech thesis.

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Abstract

Testing of Integrated Circuit (IC) is important phase in production cycle. Today’s System-on-chip (SOC) is having large complexity with number of Intellectual Property (IP) cores embedded in it. After fabrication, each IC should be tested and it requires Automatic Test Equipment(ATE). Testing cost being recurring, is dependent on the time of testing, number of test patterns, memory depth occupied by ATE, number of accessed pin of ATE etc. ATE is very expensive device. In order to bring testing cost down and ease the process of testing, there are various core standards and on-chip instrumentation like Built-in-Self Test (BIST), logic Analyzers are embedded inside each IP core by the IC designers. IEEE P1500 is one of the core standard that allow easy integration of cores and allow test reusability. IEEE P1500 test wrapper provides isolation between core and rest of design which essentially comes with easy structure for testing the core as well as the User Defined Logic (UDL) between the cores without accessing it. Scan-mux based technique is used to add Design for Testability (DFT) feature in core which provide easy access to internal nodes. Adversaries try to perform DFT based Side Channel Attacks (SCA) to extract information about secret keys used in cryptographic cores which makes security vulnerable. Due to globalization in silicon industry many fabless companies rely on the Outsource Assembly and Test Centre (OSAT) for post silicon validation and there can be trust issues between design house and test centres which can eventually result in fall in stock prices of design house. Adversaries at their end can use IEEE P1500 test wrapper to perform DFT based SCA and this brings the requirement of the securing it. Physical Unclonable Function (PUF) provides a reliable method to add security features by exploiting the physical variation in a given IC for generating keys. These secure keys earlier are stored in Non Volatile Memory (NVM). Storing secret information in NVM is quite expensive and are prone to invasive attacks, in addition to that, it requires computation of key before storing and extremely secure environment is required to burn key into NVM. On the other hand, PUF can be realized by digital circuit to generate a unique key for each device. In the project, a Secured IEEE 1500Test Wrapper (STW) is designed by leveraging property of PUF. This security additionally comes with some performance and area overhead.

Item Type:Thesis (MTech)
Uncontrolled Keywords:Physical unclonable function; IEEE P1500 standards; Scan based attacks; Hardware security
Subjects:Engineering and Technology > Electronics and Communication Engineering > Cryptography
Engineering and Technology > Electronics and Communication Engineering > VLSI
Divisions: Engineering and Technology > Department of Electronics and Communication Engineering
ID Code:9966
Deposited By:IR Staff BPCL
Deposited On:16 May 2019 19:32
Last Modified:16 May 2019 19:32
Supervisor(s):Mahapatra, Kamalakanta

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