High Throughput, Energy Efficient Network on Chip Based Hardware Accelerator

Abstract

Today, several scientific applications, in emerging domains such as bioinformatics and computational biology, like maximum likelihood based phylogenetic inference involves significant amount of mathematical computations on large floating point input data. CPU itself takes huge amount of time to do such computations. So, such applications depend upon NOC based hardware accelerators to get the high throughput and to get the results faster.

In this work, NOC based use case model is just proposed for high performance needed scientific applications. In this work, I have designed a homogeneous system to speed up the execution of mathematical computations involved in maximum likelihood based phylogenetic inference application. Homogenous system, consists of nine similar 32bit pipelined processing elements and master controller, where the communication between processing elements has not developed i.e. they can’t transfer the data between each other and each processing element can do mathematical operations like logarithmic, anti-logarithmic and dot product operations on floating point input data.

Master controller is designed to allocate the required number of available processing elements (which are not executing any task) to input tasks using breadth first search algorithm. To check the performance of a homogenous system kernels (important tasks) from the popular maximum likelihood based phylogenetic inference application have been used. Homogenous system can provide an overall throughput of nine operations per cycle with an average latency of approximately 7 clock cycles per operation.