Development of Symmetric and Asymmetric Topology for Multilevel Inverter with Reduced Number of Switches

Thakre, Kishor (2019) Development of Symmetric and Asymmetric Topology for Multilevel Inverter with Reduced Number of Switches. PhD thesis.

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An important issue with the conventional topologies for multilevel inverter (MLI) is requirement of high number of components for increase in number of voltage levels. Efforts are being made to reduce number of component, especially the number of power switches in multilevel inverter topologies so that they can also be effectively employed for low power applications. In addition to high power DC to AC conversion requirements. A background of research pertaining to the evolution of novel topologies for multilevel inverters is described in this thesis. Recent topologies reported in the literature with an objective of reducing the component count for high number of voltage levels. Attempts in evolving newer topologies lead to certain compromises to be made; thereby limiting the characteristics of the topology in terms of voltage ratings of power switches, asymmetry in input DC source configurations, modularity and so on. In this thesis, topological solutions for MLI have been sought so that reduction in number of power switches is achieved while preserving some main characteristics of multilevel inverter.
Prior to the discussion on topologies proposed in this thesis, which form the primary contribution of this work, a so-called switching control scheme with voltage level based modulation for multilevel inverters is developed so as to modulate any given topology with voltage-level based modulation techniques. Mathematical description of the scheme is presented. In addition, symmetric MLI has been investigated for charge balance control using the proposed modulation scheme. Validations are carried out based on simulation studies.
Six modified topologies (topology-I, topology-II, topology-III, topology-IV, topology-V, and topology-VI) are presented in this thesis. Topology-I and topology-II named as basic unit cell based symmetrical MLI, which can be operated with or without H-bridge. Topology-III named as cascaded sub MLI, which can be operated as symmetrical and asymmetrical source configuration. Also, an algorithm for asymmetric source configuration is presented since the popular configurations cannot be used with topology-III. Topology-IV named as asymmetrical cascaded MLI based on modular structure, it operate its own asymmetric source configuration. Topology-III and Topology-IV has one main limitation: it requires a mix of unidirectional-blocking-bidirectional conducting and bidirectional-blocking-bidirectional-conducting switches. Two more topologies (topology-V and topology-VI) for MLI based on series connection of basic unit cells. However, the basic unit cells are different for both topologies. Both topologies can be operated in symmetric and asymmetric source configuration. In order to generate high number of voltage levels, several methods are directed in determining the magnitude of input dc voltage source for asymmetric MLI. The working principles of the proposed topologies are explained and important mathematical formulations are presented. The performances of the proposed topologies are verified through simulation and experimental results.

Item Type:Thesis (PhD)
Uncontrolled Keywords:Diode clamped inverter; Flying capacitor inverter; Cascaded H-bridge inverter
Subjects:Engineering and Technology > Electrical Engineering > Power Transformers
Engineering and Technology > Electrical Engineering > Power Electronics
Divisions: Engineering and Technology > Department of Electrical Engineering
ID Code:10083
Deposited By:IR Staff BPCL
Deposited On:18 Mar 2020 16:05
Last Modified:18 Mar 2020 16:05
Supervisor(s):Mohanty, K B

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