Design and Implementation of High Performance Current Steering DACs using On-Chip Enhancement Technique

Abstract

The future generation (6G) machine type communication (MTC) enabled IoT devices gain massive attention in recent years. The wireless IoT devices utilize the emerging low power wide area networks (LPWAN) technologies. These technologies are extremely energy and cost efficient and suitable for providing long range connectivity. Most of these IoT devices are used in smart city, smart village, air quality measurement, ecological surveillance, smart industrial and agricultural applications etc. These demanding applications require uninterrupted communication between devices. For the simultaneous transmission and reception of the signals, these high end devices explicitly use complex transceiver units. To interface with the real analog signals, the transceiver unit utilizes the system-on-chip (SoC) digital to analog converter (DAC), which is the vital component for the signal processing. In this context, the IoT devices require a low-to-medium resolution (i.e., 6 to-12-bit) high performance DAC with a sampling frequency below 1 GHz for direct conversion and transmission of data. Current steering DAC (CS-DAC) is one of the most promising DAC architecture to meet these requirements. The intrinsic advantages like fast switching and low output node driver make CS-DAC structures more suitable for high speed and wide band transmitters. The effectiveness of these CS-DACs are determined on the basis of static and dynamic performance parameters. The spurious free dynamic range (SFDR) is one of such important performance metric, which is used to measure the linearity of the CS-DACs. Although, the CS-DACs suffer from performance degradation at high frequencies due to process and technology mismatches and other non-idealities. All of these effects make it very challenging to design a high performance CS-DAC. In this work, the major CS-DAC non-ideal error sources like amplitude mismatch and code dependent load variation (CDLV) effects are analyzed and to address these effects, three enhancement techniques are proposed. To mitigate the amplitude mismatch errors, novel dynamic element matching (DEM) techniques like pair wise swap enabled DEM (PSER-DEM) and fully random rotation based DEM (FRR-DEM) are proposed. Additionally, an on-chip partial self-healing technique is implemented to improve the linearity of the CS-DAC by reducing the amplitude mismatch effect. A code independent output impedance compensation (CIIC) technique is proposed to reduce the CDLV effect. To verify these techniques, three 10-bit CS-DACs are designed using 180 nm CMOS process technology followed by rigorous mismatch based simulations at 500 MHz sampling frequency. Further, a 6-bit CS-DAC is implemented in 180 nm CMOS process and tested to validate the proposed PSER-DEM technique. More than 6 dB improvement in SFDR is observed from the measurement results for PSER-DEM enabled DAC. Similarly, on chip partial self healing method shows 3.5 LSB improvement in INL value from the mismatch based simulation. The partial self-healing assisted PSER-DEM technique is presented to design a robust hybrid CS-DAC to enhance both static and dynamic performances to achieve better FOM values. A comparative assessment of the proposed methods are performed, which exhibit better performances with improved Figure-of-Merit (FOM), compared to the state-of-the-art CS-DAC architectures.