P S, Arun Kumar (2009) Implementation of Image Compression Algorithm using Verilog with Area, Power and Timing Constraints. MTech thesis.
Image compression is the application of Data compression on digital images. A fundamental shift in the image compression approach came after the Discrete Wavelet Transform (DWT) became popular. To overcome the inefficiencies in the JPEG standard and serve emerging areas of mobile and Internet communications, the new JPEG2000 standard has been developed based on the principles of DWT. An image compression algorithm was comprehended using Matlab code, and modified to perform better when implemented in hardware description language. Using Verilog HDL, the encoder for the image compression employing DWT was implemented. Detailed analysis for power, timing and area was done for Booth multiplier which forms the major building block in implementing DWT. The encoding technique exploits the zero tree structure present in the bitplanes to compress the transform coefficients.
|Item Type:||Thesis (MTech)|
|Uncontrolled Keywords:||Verilog Implementation,Image Compression, Algorithm|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > VLSI|
Engineering and Technology > Electronics and Communication Engineering > Image Processing
|Divisions:||Engineering and Technology > Department of Electronics and Communication Engineering|
|Deposited By:||Arun Kumar P S|
|Deposited On:||28 May 2009 11:08|
|Last Modified:||28 May 2009 11:08|
|Supervisor(s):||Mahapatra, K K|
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