A Novel High Speed Dynamic Comparator with Low Power Dissipation and Low Offset

Velagaleti, Silpakesav (2009) A Novel High Speed Dynamic Comparator with Low Power Dissipation and Low Offset. MTech thesis.



A new fully differential CMOS dynamic comparator using positive feedback suitable for pipeline A/D converters with low power dissipation, low offset, low noise and high speed is proposed. Inputs are reconfigured from typical differential pair comparator such that near equal current distribution in the input transistors can be achieved for a meta stable point of the comparator. Restricted signal swing clock for the tail current is also used to ensure constant currents in the differential pairs. Nearly 18mV offset voltage is easily achieved with the proposed structure making it favorable for flash and pipeline data conversion applications. The proposed topology is based on two cross coupled differential pairs positive feedback and switchable current sources, has a small power dissipation, less hysteresis band, less area, and it is shown to be very robust against transistor mismatch, noise immunity. Test structures of the comparators, designed in GPDK 90 nm are measured to determine offset power dissipation and speed with 1.8 V are compared and the superior features of the proposed comparator are established.

Item Type:Thesis (MTech)
Uncontrolled Keywords:Offset,Power dissipation,Dynamic comparator,Positive feedback
Subjects:Engineering and Technology > Electronics and Communication Engineering > VLSI
Divisions: Engineering and Technology > Department of Electronics and Communication Engineering
ID Code:1376
Deposited By:Silpakesav Velagaleti
Deposited On:28 May 2009 11:24
Last Modified:28 May 2009 11:24
Supervisor(s):Mahapatra, K K

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