Hardware Implementation of Densely Packed Decimal Encoding

Abstract

Binary Coded Decimal ( BCD ) in which four bits are used for each decimal digit is a widely used encoding for decimal data .Decimal arithmetic and shifting are simplified by using operands in this form, and both rounding to a specified number of digits and conversions to or from characters are trivial. For the storage and simple manipulation of decimal data, BCD remains an appropriate encoding to use. In some situations, however, a more compact representation offers significant advantages. Decimal floating-point numbers in a compact form can be used to implement the requirements of the IEEE 854 standard and meet the increasing demands for decimal arithmetic in applications.
An efficient encoding scheme for decimal data is described by Chen and Ho.Chen Ho encoding is a lossless compression of three decimal digits coded in BCD into 10 bits using an algorithm which can be applied or reversed using only simple Boolean operations. Densely Packed Decimal (DPD) is an refinement of the Chen ho encoding. It gives the same compression and speed advantages but is not limited to multiples of three digits. The DPD encoding allows arbitrary-length decimal numbers to be coded efficiently while keeping decimal digit boundaries accessible. This results in efficient decimal arithmetic and makes the efficient and optimized use of available resources such as storage or hardware registers.
This thesis embodies the work done to implement the Densely Packed Decimal (DPD) encoding on hardware using digilent board containing VIRTEX-II Pro FPGA.