Design of FFT processor

Jain, Pavan Kumar and Md., Anish (2012) Design of FFT processor. BTech thesis.



In this project our goal is to design a processor for implementation of FFT Algorithm in FPGA. A Digital Signal Processor with specific instruction sets and meant for a specific application is called as Application Specific Instruction set Processor (ASIP). An ASIP is widely used as a System on a Chip Component. Application Description Languages (ADLs) are nowadays becoming popular because of its quick and optimal design convergence achievement capability during the design of ASIPs. The first stage of designing a processor is Architecture Design Implementation.

LISA ( Language For Instruction Set Architecture) is the ADL which has been used here. The platform used for design is CoWare, which allows processor architecture to be defined at an abstract level . In a similar approach to implement the processor in Hardware Description Language( here we have used VHDL), we have to make use of floating point arithmetic. This has been achieved with the help of IP cores from IP Core Generator in Xilinx ISE 10.1.

Discrete Fourier Transform is of much importance in fields of signal processing. A dedicated hardware for the frequency domain analysis of physical signals has become necessary in a large part of the electronics industry. FFT (Fast Fourier Transform) is the method of efficient calculation of DFT of a signal. It has an improved computational efficiency with respect to space and time complexity. We have implemented the 8 point radix 2 and 16 point radix 4 Cooley-Tukey algorithm in VHDL.

Item Type:Thesis (BTech)
Uncontrolled Keywords:ASIP, FFT, RADIX-2, RADIX-4, LISA, PIPELINE, VHDL
Subjects:Engineering and Technology > Electronics and Communication Engineering > VLSI
Engineering and Technology > Electronics and Communication Engineering > Signal Processing
Divisions: Engineering and Technology > Department of Electronics and Communication Engineering
ID Code:3470
Deposited By:Mr. Pavan Kumar Jain
Deposited On:23 May 2012 15:56
Last Modified:23 May 2012 15:56
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Supervisor(s):Mahapatra, K K

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