Das, Abhishek and Dash, Suraj (2012) Design and Implementation of FPGA based linear All Digital Phase-Locked Loop for Signal Processing Applications. BTech thesis.
This project presents a linear all-digital phase locked loop based on FPGA. In this ADPLL the phase detection system is realized by generating an analytic signal using a compact implementation of Hilbert transform and then simply computing the instantaneous phase using CORDIC algorithm in vectoring mode of operation. A 16-bit pipelined CORDIC algorithm is employed in order to obtain the phase information of the signal. All the components used in this phase detection system are realized as digital discrete time components. This design does not involve any class of multipliers thus reducing the complexity of the design. The loop filter of the ADPLL has been designed using PI controller which has a low pass behavior and is used to discard the higher order harmonics of the error signal. The CORDIC algorithm in its rotation mode of operation is used to compute sinusoidal values for the DDS. The ADPLL model has been implemented using Xilinx ISE 12.3 and ModelSim PE Student Edition 10.1a. The ADPLL model describes a novel method of implementation of CORDIC algorithm for the DDS system. This ADPLL model basically used for synchronization of closed loop RF control signals in a heavy ion particle accelerator can be implemented even in an ASIC which can be seen with a more general use for many a applications in the daily life.
|Item Type:||Thesis (BTech)|
|Uncontrolled Keywords:||All Digital Phase-Locked Loop, Hilbert Transform, CORDIC algorithm, PI Controller, Direct Digital Synthesizer, FPGA implementation.|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > VLSI|
Engineering and Technology > Electronics and Communication Engineering > Signal Processing
|Divisions:||Engineering and Technology > Department of Electronics and Communication Engineering|
|Deposited By:||Abhishek Das|
|Deposited On:||04 Jun 2012 11:34|
|Last Modified:||20 Dec 2013 15:13|
|Supervisor(s):||Sahoo, A K and Babu, B C|
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